The use of an assembly of electrical conductors known as "bus" is common in electrical circuit designs. As shown in FIG. 1, a bus 1, which may be referred to as a system bus, is an electrical, mechanical and functional unit widely used in a multiprocessor system including a plurality of agents, such as main processor units (MPU) 2, shared memory units (SMU) 3, input/output processor units (IOU) 4 and system control units (SCU) 5, for connecting signal lines among the agents, each agent being coupled to the system bus 1.
Using a shared approach, signal lines of the system bus are used, when available, by various agents in the multiprocessor system. To avoid bus contention, which arises when two or more agents request access to a same signal line simultaneously, a bus arbiter is provided typically for determining which one of the agents will be allowed to have the access to the signal line, according to some specified access criteria. Then, the agent gaining the access to the system bus transfers address and/or data according to a predetermined transfer protocol.
Both the bus arbitration and the data transfer of all of the agents may be synchronized with a system bus clock signal. The system bus clock signal may be transmitted from a backboard to each agent through a separate signal line. In order to obtain a high data transfer rate, it may be desirable to use a high frequency bus clock, since the system performance depends on the data transfer rate, which, in turn, depends on the frequency of the system bus clock with which the bus operation, including the bus arbitration and data transfer, is synchronized.
However, the frequency of the system bus clock is restricted by the so-called bus arbitration period. The bus arbitration period, as used herein, represents a period between a time for detecting one or more bus request signals each of which is asserted by an agent requesting an access to the system bus and a time at which the winning agent assumes bus mastership. Consequently, in order to increase the bus clock frequency, it is often necessary to arbitrate the system bus for multiple periods of the bus clock in the multiprocessor system.